How are you delivering the data to the drivers? Here is the configuration used:. There is is a small delay between bytes, but nowhere near as large as 64us. I tried to recreate the problem you describe, but I wasn’t able to exactly. Are you sure that USB side is sending data fast enough?
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Here are some things to check. Here is the configuration used:. I have no idea how fast the Rt232hl transmit the data. As written on the message, no matter how many bytes sent at once, the delay is same.
USB peripherals can slow to a crawl if they only get a byte or few moved per frame. If this is a custom board design, or you bought a discount FTH adapter board, make sure it has the correct system clock ft232hp. I check the Ftsi side because that’s the end of the line and I can easily check with logic ft232ul.
In what size chunks? Note that for SPI it doesn’t matter if the clock is stretched a little bit here and there since it is based on the edges of the clock signal read on one edge, propagate on the other. Here is the configuration used: Why are you looking only at SPI side of your bridge? I imagined maybe playing with the channelConf. I have it set tobut often for ft232ho sensitive stuff, I have it lower 2 Try a slower clockrate first just to test and make sure the device is communicating correctly I assume you did, I’m just adding this in case someone else hasn’t tried that yet.
usb – FTHL FTDI consecutive SPI bytes delay problem – Electrical Engineering Stack Exchange
I’m still surprised some people can reach high transfer speeds out of the box and using the provided lib. Email Required, but never shown. I heard back from FTDI guys, they suggest I don’t use their library but they didn’t clearly say that their lib was bugged. Are you sure that USB side is sending data fast enough? Also, delay between bytes should be a setting somewhere.
I’ve tried other length, etc no change. This is what it looked like on my logic analyzer when I output 6 bytes at once at a clock rate of 5MHz. GCC Library and code from: There must be something to fix because there are numerous examples of ftfi reaching high transfer rates.
That delay between bytes is based on how long it ft232hk the chip to move the next byte from its internal buffer to the output shift registers.
However, between each byte, there is a 64uS delay so it means that no matter how high is the SPI clock, the data transfer takes minutes instead of seconds. I did check with a logic analyser, the bytes are correctly sent out and the SPI clock match the settings.
If the chip is clocked slowly, then this will show at the higher frequencies as a larger gap between bytes. LatencyTimer would help, but it shows no difference no matter the value used 10, delay remain 64uS between consecutive bytes.
There is is a small delay between bytes, but nowhere near as large as 64us. I’ve used sample code provided with sample-dynamic.